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TMGG12864AU

Format: 128 * 64 dots
LCD Mode: FSTN, Positive, B&W, Transflective
Viewing Direction: 6 o'clock
Driving Scheme: 1/65 Duty cycle, 1/9 Bias
Single Supply Voltage: Power supply voltage range (VDD): 3.0~3.6V
Low current sleep mode
64 level of Internal Contrast Control and External Contrast Control
8-bit 68/80-series Parallel or 4-wire SPI Interface
Vertical Scrolling, Display offset control and RAM Page blinking
On-chip DC-DC Converter, 2X,3X,4X booster
Product Details
Interface
Mechanical Spec.
Full Spec.
Resolution 128 * 64 Dots Module Size (mm) 50.40 * 51.20
Viewing Area (mm) 49.00 * 38.00 Character Size/Dot Pitch (mm) 0.35 * 0.54
Dot Size (mm) 0.32 * 0.51 Type COG
Connection FPC IC IST3931 or equivalence
Display Mode +Ve or -Ve/ STN, FSTN, FFSTN Backlight Color YG, R, G, B, W

Pin no.

Symbol

Function

1

IRS

This terminal selects the resistors for the V0 voltage level adjustment

IRS=”H”: Use the internal resistors

IRS=”L”: Do not use the internal resistors

2

PS

Parallel or Serial Interface. “H”: Parallel; ”L” Serial

3

C86

MPU interface select I/O

“H”:=6800 series; “L”:=8080 series

4

VR

Voltage adjustment pad. Applies voltage between V0 and VSS using a resistive divider.

5

V0

LCD driver suppliers voltages. The voltage determined by the LCD cell is

impedance-converted by a resistive driver or an operation amplifier for

application. Voltages should be according to the following relationship:

V0V1V2V3V4VSS2

6

V4

7

V3

8

V2

9

V1

10

CAP2-

Capacitor 2- pad for internal DC/DC voltage converter

11

CAP2+

Capacitor 2+ pad for internal DC/DC voltage converter

12

CAP1+

Capacitor 1+ pad for internal DC/DC voltage converter

13

CAP1-

Capacitor 1- pad for internal DC/DC voltage converter

14

CAP3+

Capacitor 3+ pad for internal DC/DC voltage converter

15

VOUT

DC/DC voltage converter output. Connect a capacitor between this terminal and VSS

16

VSS

Ground (0)

17

VDD

Power supply pin. (3.3V)

18

D7(SI)

When the serial interface is selected (P/S=” L”), then D7 serves as the serial data input terminal

(SI) and D6 serves as the serial clock input terminal (SCL).

When the serial interface is selected, fix D0~D5 pads to VDD or VSS level.

When the chip select is inactive, D0 to D7 are set to high impendence.

19

D6(SCL)

20

D5

21

D4

22

D3

23

D2

24

D1

25

D0

26

/RD(E)

6800 series: enable clock input pin

8080 series: “L” read select enable pin

27

R/W

6800 series: “H”: read, “L”: write; 8080 series: “L” write select

28

A0

Display/control data select “H”: display data; “L”: control data

29

/RES

Reset signal input

30

/CS1

Chip select input pin active when /CS1 is low


TMGG12864AU-01-CDA00.pdf


TMGG12864AU-01-SPA00.pdf


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